The invention relates generally to electrical circuits, and more particularly to synchronization and timing circuits.
A clock source can be used to synchronize communications among plural electrical circuit elements. For example, a clock source can be used in conjunction with a communications bus to provide a synchronous communications link between a sourcing and a receiving device. A source synchronous communications bus can be used to couple a source device to one or more receiving devices. In a source synchronous communications link, the source device provides a sourcing clock signal that can be used by a receiving device to synchronize the reading of data from the communications link.
Electrical designs for mission critical systems must provide reliability. Redundancy can be built into a mission critical system to provide a measure of reliability. For example, a system designer may provide a design that includes a master system that is supported by a fully redundant slave system. In the event a failure arises in the master system, the slave system can be utilized to support system requirements. However, the transition from the master system to the slave system can cause problems. Depending on the system design requirements, the slave system may be required to take over immediately so that no down time is experienced. Alternatively, the master system may need to be taken off line prior to the starting of the slave system. Information may be required to be shared between the master and slave system in order to support the transition. Timing and control issues and glitches are some of the problems that must be resolved when introducing redundancy to a system.
In one aspect, the invention provides a redundant clock controller that includes a first input operable to receive a first clock signal having a first frequency, a first output operable to couple the first clock signal to a receiving device, a second input operable to receive a second clock having a same frequency as the first clock signal but of arbitrary phase, a second output and a variable delay line coupling the second clock signal to the second output.
The second output is operable to couple a delayed version of the second clock signal to the receiving device. The redundant clock controller includes a comparator receiving as an input the first and the second clock signals and providing as an output to the variable delay line a control signal for adjusting a delay in the second clock signal so as to match a phase of the first clock signal received at the receiving device.
Aspects of the invention can include one or more of the following features. The variable delay line can include a delay that can be adjusted to be greater than a period of the first clock signal. The first clock frequency can be set to approximately 19.44 MHz and the delay can be adjusted up to 70 nanoseconds.
The redundant clock controller can include a first output circuit coupling the first clock signal to the first output, and a second output circuit coupling the delayed version of the second clock signal to the second output, wherein each of the output circuits includes means for disabling the transmission of a respective clock signal to the receiving device. The output circuit can include a divider circuit for producing a lower frequency clock signal from a respective clock signal. The first clock frequency signal can be approximately 19.44 MHz and the lower clock frequency signal can be approximately 8 kHz. The divider can include a down counter operable to receive a clock signal of a high frequency and output a signal of a lower frequency, wherein the lower frequency level is determined by a count value that is loaded into the down counter after each reset.
The redundant clock controller can include a coarse alignment circuit operable to monitor the phase difference between the two low frequency clock signals generated by the respective output circuits wherein the count value is varied depending on the phase difference between the two low frequency clock signals. The count value can be varied between 1213 and 1214 counts.
The redundant clock controller can include a first phase locked loop coupled between the variable delay line and the second output operable to low pass filter glitches introduced by the variable delay line circuit.
The redundant clock controller can include a second variable delay line coupled between the first input and the first output, a second comparator receiving as an input the first and the second clock signals and providing as an output to the second variable delay line a second control signal for adjusting a delay in the first clock signal so as to match a phase of the second clock signal received at the receiving device, a selector for selecting one of either the first or the second clock signals as a master clock signal and a means for disabling the delay imparted from the variable delay line in the signal path for the master clock signal.
The redundant clock controller can include a phase locked loop in line between each variable line delay and a respective output. The phased locked loop can be operable to provide a low pass filter for glitches introduced by a variable delay line to a respective clock signal.
The comparator can include a counter, a phase comparator and a controller. The phase comparator receives as inputs each of the first and second clock signal and provides as an output an indication of a relative phase difference between the two clock signals. The output of the phase comparator is coupled to the input of the counter. The counter is operable to evaluate the indication received from the phase comparator and provide as an output a count that reflects a change in the delay provided by the variable delay line so as to minimize the phase difference between the first and second clock signals. The output of the counter is coupled to the input of controller. The controller is operable to program the variable delayline to set the delay for the second clock signal.
In another aspect the invention provides a method for providing a redundant clock signal to a receiving device and includes providing first and second frequency source signals, each of the first and second frequency source signal being of a same frequency but of arbitrary phase. The method includes comparing the first and second frequency source signals to determine a phase difference between the first and second frequency source signals and selecting one of the first and second frequency source signals as a master clock signal, the other being a slave clock signal. If a phase difference is detected, the method sets a delay in the slave clock signal so as to align the phase of the slave clock signal to the master clock signal. The master clock signal is provided to a receiving device. The method includes switching upon a predetermined event and providing the slave clock signal to the receiving device without introducing glitches in the switchover.
In another aspect the invention provides a clock controller that includes a first input operable to receive a first clock signal having a first frequency, a second input operable to receive a second clock having a same frequency as the first clock signal but of arbitrary phase, a first output and a variable delay line coupling the first clock signal received at the first input to the first output. The first output is operable to couple a delayed version of the first clock signal to the receiving device. The clock controller includes a comparator receiving as an input the first and the second clock signals from the first and second inputs and providing as an output to the variable delay line a control signal for adjusting a delay in the first clock signal so as to match a phase of the second clock signal received at the receiving device.
Aspects of the invention can include one or more of the following advantages. A system is provided for aligning two frequency sources of arbitrary phase to produce a redundant clock controller system that meets the stringent requirements of GR-1244-CORE for the maximum time interval error (MTIE) and mean phase error (TDEV).